library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity transformacion is
Port ( --clk : in STD_LOGIC;
CRI : in std_logic;
smap : in std_LOGIC;
busdatosbaja : in std_logic_vector (7 downto 0);
M : out std_logic_vector (11 downto 0));


end transformacion;
architecture Behavioral of transformacion is
constant x : std_logic_vector := "ZZZZZZZZZZZZ";
constant y : std_logic_vector := B"0000";--poner esta parte para el camino 3 de la carta asm
shared variable z: std_logic_vector (11 downto 0);
begin
--process (clk,smap)
process(smap)
begin
			if(smap='1')
				then M <= x;
			elsif (smap='0')
				then M <= z;
			else M <= x;	
			end if;

end process;
process(cri)
begin
			if(cri='1')
				then z := x;
				elsif (cri='0')
					then z := busdatosbaja & y;
				else z := x;
	
			end if;

end process;


end Behavioral;